Testability of an electrical circuit is a design characteristic that generally allows for the status (normal, inoperable, degraded) of a device to be determined and the isolation of faults within the device to be performed quickly to reduce both the test time and cost. Design for testability techniques are design efforts employed to ensure that a device is testable.
One of two attributes related to testability is controllability which is the ability to establish a specific signal value at each node in a circuit by setting values on the circuit's inputs. The other attribute is observability which is the ability to determine the signal value at any node in a circuit by controlling the circuit's inputs and observing its outputs.
The observability and controllability of an electrical circuit may usually be enhanced through the utilization of test points. Additionally, a scan register having both shift and parallel-load capability can be utilized to enhance observability and/or controllability.
The storage cells within the scan register are usually used as observation points and/or control points. A scan register may include a plurality of multiplexed scan data flip flops to form a plurality of storage cells.
A logic chip 10 having combinational logic 8 and sequential logic 9 is shown in FIG. 1. Combinational logic 8 is coupled with a plurality of parallel inputs 11 and a plurality of parallel outputs 12. The sequential logic 9 may comprise a plurality of storage cells 20 as shown in FIG. 1. A clock 7 produces a clock signal which synchronizes the storage cells. The storage cells 20 may include classical (normal) data flip-flops.
Referring to FIG. 2, a prior art data flip-flop 30 is shown. The data flip-flop 30 includes a single data input 32, clock signal input 33, first data output 34 and an inverted data output 35. The classical data flip flop 30 includes a first latch 36 and second latch 37 for storing data.
A plurality of signals 14, 15, 16 are applied from the combinational logic 8 to the sequential logic 9 as shown in FIG. 1. The signals 14, 15, 16 are difficult to observe because they drive D inputs of the respective data flip-flop storage cells 20 and the signals can only be observed at the parallel outputs 12. A plurality of signals 17, 18, 19 are applied from the sequential logic 9 to the combinational logic 8. The signals 17, 18, 19 are difficult to control because they are driven by data flip-flop storage cells 20 and only the parallel inputs 11 can be directly controlled.
The utilization of multiplexed scan data flip-flops was introduced in the prior art to enhance observability and controllability. FIG. 3 shows a block diagram of a logic chip 10a coupled with a plurality of parallel inputs 11 and a plurality of parallel outputs 12. Like numerals from the first described embodiment are utilized where appropriate with any significant difference being indicated with the suffix "a" or with different numerals. A scan register 13 having a plurality of storage cells 20a including scan data flip-flops is shown coupled with the combinational logic 8. The scan flip-flop storage cells 20a may be utilized to observe signals 14, 15, 16 and control signals 17, 18, 19.
Scan data flip-flop storage cells 20a may be loaded with data from two data sources. During a normal mode of operation, data signals from the combinational logic 8 may be loaded via signals 14-16 into respective data inputs (each generally referred to as "D"). During a scan mode of operation, data may be loaded into the first scan data flip-flop storage cell 20a from the scan data input 22 via a scan data input port (generally referred to as "SD"). During a data shift operation, the output data of the first scan data flip-flop storage cell 20a may be loaded into the next scan data flip-flop storage cell 20a at the next clock cycle.
A scan mode control 21 provides a scan control signal to a scan control input (generally referred to as "SC" or a data control input) of each scan data flip-flop storage cell 20a for selecting the mode of operation of the scan data flip-flop storage cells 20. Usually the data control signal from scan mode control 21 is a logic low signal during the normal mode of operation and logic high signal during the scan mode of operation.
A scan register 13 may load data in parallel during the normal mode of operation and shift data during the scan mode of operation. Loading data into the scan register 13 during a scan mode of operation is generally referred to as a scan-in operation and reading data out of the scan register is generally referred to as a scan-out operation. Responsive to a scan mode of operation being selected, the output of each scan data flip-flop storage cell 20a in the scan path becomes a pseudo input to the combinational logic 8 thereby improving controllability. The input of each scan data flip-flop storage cell 20a within the scan path becomes a pseudo output of the combinational logic 8 thereby improving the observability of the logic chip 10.
More specifically, the scan data flip-flop storage cells 20 may input data via signals 14-16 when the scan register 13 is utilized to observe the data within the combinational logic 8. The scan mode control 21 operates the inputting of data via signals 14-16. Subsequently, the data inputted via signals 14-16 may be scanned out of the scan register 13 into a scan data output 23 responsive to a scan out data control signal from scan mode control 21. Thereafter, the data may be analyzed to observe the operation of the combinational logic 8 of the logic chip 10.
The scan mode control 21 also operates the inputting of data into the logic chip 10 for controlling signals 17-19. More specifically, data available at scan data input 22 may be read into the scan flip-flops 20 within the scan register 13 responsive to a data control signal from scan mode control 21. Thereafter, the scan-in data may be inputted into the combinational logic 8 via signals 17-19 thereby improving the controllability of the logic chip 10.
A conventional multiplexed scan data flip-flop 40 which has been utilized to comprise each of the storage cells 20 within a scan register 13 is shown in FIG. 4. The multiplexed scan data flip flop 40 includes a clock input 42 for providing synchronized operation.
The multiplexed scan data flip-flop 40 additionally includes a first data input 43 and a second data input 44. The first data input 43 (also referred to as normal data input) and second data input 44 (also referred to as a scan data input) are coupled with an internal multiplexer 46 within the multiplexed scan data flip-flop 40. The multiplexer 46 is coupled with a first latch 47 within the multiplexed scan data flip-flop 40. A scan control 45 operates the internal multiplexer 46 for controlling the application of data signals via one of the first data input 43 and second data input 44 to the first latch 47. More specifically, a data signal is introduced into the first latch 47 via the first input 43 during a normal mode of operation and the second input 44 during a scan mode of operation.
However, the utilization of multiplexed scan flip-flops have introduced performance drawbacks which include variations of setup and hold times and susceptibility to clock skew within the scan chain. The clock skew problem may be alleviated somewhat by providing additional delays within the scan chain. However, the setup time and hold time variations are caused by delays through the internal multiplexers within the multiplexed scan flip-flops and such variations present a critical problem.
A conventional approach to solve the setup time and hold time variations has included the utilization of an unbalanced multiplexer by providing large devices in the normal data path. However, this solution still has an inherent performance degradation and requires additional space for implementing the unbalanced multiplexer.
Therefore, a need exists for providing a scan flip-flop which provides reduced or minimized timing performance degradation within the normal data path.